Avsnitt
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Austin and Vik discuss their recent experience at Computex, where they met for the first time in person after six months of podcasting together.
They share insights about the massive show, the people they connected with, and the exciting developments in AI hardware and interconnect technology.
Connect with Vik and Austin via a daily free newsletter:
https://www.semidoped.com
Vik's Paid Substack: https://www.viksnewsletter.com
Austin's Paid Substack: https://www.chipstrat.com
Chapters
00:00 Meeting in Person for the First Time
03:05 Experiencing Computex: A Massive Show
05:17 Connecting with the Audience: Real-Life Encounters
06:46 Networking with Industry Leaders
10:42 Keynote Highlights: Marvell's Vision
15:11 The Future of Interconnects: CPO and Beyond
22:54 Exploring Optical Interconnects and Future Technologies
25:56 Micro LED Developments and Future Conferences
27:34 Power Innovations in Data Centers
30:54 Intel's Keynote and New CPU Technologies
36:31 Intel Foundry's Advancements and Industry Implications -
Huawei dropped a paper claiming 1.4nm-class performance without EUV, and the internet immediately declared ASML dead and US export controls useless. Austin and Vik recorded one day after Memorial Day to unpack what Huawei actually announced at ISCAS 2026 — and why the "EUV killer" headline gets the story backwards.
They walk through the tau scaling law (tau is delay, and the idea is to attack it at the system level instead of the transistor), logic folding via hybrid bonding, the Kirin 2026 that doubles transistor count without shrinking, and who can actually manufacture stacked logic. Then the other tau knobs: a unified memory bus and near-packaged optics. Along the way: BESI vs EV Group, die-to-wafer vs wafer-to-wafer bonding, and why hybrid bonding isn't export-controlled the way EUV is.
The takeaway is the opposite of the headline. Tau scaling is rational engineering under constraint, it's bullish for ASML (two DUV wafers per product, not fewer), and the moment EUV-enabled fabs stack their own advanced-node wafers, the gap widens instead of narrowing. Bullish advanced packaging, bullish EDA and multiphysics.
Chapters:
0:00 The "EUV killer" paper that broke the internet
2:28 What Huawei actually announced at ISCAS
4:00 Tau scaling: optimize delay, not transistors
8:58 The equation and the 10x AI claim
11:05 Logic folding: stacking logic on logic
17:24 Who builds it, and can hybrid bonding be banned?
24:16 Why this is bullish for ASML
29:49 The other tau knobs: memory and optics
35:18 Takeaways: packaging, EDA, multiphysics
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Newsletter: https://www.chipstrat.com
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Newsletter: https://www.viksnewsletter.com
X: https://x.com/vikramskr -
Saknas det avsnitt?
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Spend one hour here and you've caught up on the entire arc of semiconductor lithography. Austin and Vik run a masterclass on the technology that decides who gets to make leading-edge chips, and why so few companies can afford to.
The thread is economics. An EUV machine runs about $400 million, a new fab needs roughly 15 of them, and the total bill clears $20-30 billion before a single wafer ships. Austin and Vik trace the whole story: Rock's Law and the cost of a fab, what it actually takes to build one, the evolution from 193nm DUV through multi-patterning to 13.5nm EUV, how ASML generates EUV light by exploding falling tin droplets, and the move to high NA and its mirrors. Along the way, the fun history — i-line, krypton fluoride, immersion lithography, and the engineer who started it all by flipping a microscope upside down.
Then the part that matters most: where lithography goes next. Two startups, xLight and Substrate, are attacking the cost problem from first principles. xLight wants to decouple the light source from the scanner with a free-electron laser and sell photons as a service. Substrate wants to skip EUV entirely and revive X-ray lithography. If either works, the economics of who can build a fab change completely.
Chapters:
0:00 The 13F panic, and today's topic
2:23 Why the real story is economics, not physics
6:18 Austin in the clean room: graphene and bunny suits
10:06 Rock's Law and the $20 billion fab
18:08 DUV, the Sharpie, and a history of light
24:58 Multi-patterning, explained with a football field
34:45 How EUV makes 13.5nm light from tin droplets
41:14 High NA, anamorphic optics, and the half-field tax
46:45 The startups rethinking lithography: xLight and SubstrateRelevant reading:
Chipstrat — The economics of lithography: https://www.chipstrat.com/p/lithography-economics
Chipstrat — xLight and photons as a service: https://www.chipstrat.com/p/photons-as-a-service
Chipstrat — Substrate and X-ray lithography: https://www.chipstrat.com/p/substrate
Vik's Newsletter — the viability of X-ray lithography: https://www.viksnewsletter.com/p/an-in-depth-look-at-the-viability
Fred Chen — LELE multipatterning and EUV stochastics (Substack): https://frederickchen.substack.com/p/can-lele-multipatterning-help-against
Chip War, Chris Miller
Focus, Marc Hijink (the ASML book): https://www.amazon.com/Focus-Inside-struggle-complex-machine-ebook/dp/B0CW1FLCD4Follow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/chipstratFollow Vik:
Newsletter: https://www.viksnewsletter.com/
X: https://x.com/vikramskrFollow Semi Doped:
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Cerebras IPO is the only thing to talk about this week. 🔥
IPO prices at $185/share. Pops nearly 70% right after. The first wafer-scale chip company to make it public — after a 40-year curse killed every prior attempt.
A water-cooler-style convo on what Cerebras actually builds, why a 23 kW wafer is a power and cooling nightmare, why 44 GB of SRAM is both the magic and the wall for LLM inference, and the cursed Trilogy Systems saga that Gene Amdahl tried — and failed — to pull off in 1983.
Why does Cerebras leave the whole wafer intact instead of dicing it? How do they route around defects to harvest ~900K working cores out of ~1M? Why is power delivery vertical, and why does the wafer literally expand a tenth of a millimeter when it heats up? What does the OpenAI deal actually buy — wafers, or tokens? And why does that distinction matter?
Chapters:
0:00 Cold open: 23 kW per wafer
0:15 Cerebras IPO day at $185
2:39 What's a wafer-scale engine
10:30 Power, cooling, and thermal expansion
18:12 The 44 GB wall
26:35 The Trilogy Systems curse
32:11 Supercomputing → training → inference
39:36 The OpenAI deal and the Wild WestRelevant reading:
Vik's Substack post on the Cerebras IPO and OpenAI deal: https://www.viksnewsletter.com/Follow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/austinsemisFollow Vik:
Newsletter: https://www.viksnewsletter.com/
X: https://x.com/vikramskrFollow Semi Doped:
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Gimlet Labs runs an inference cloud built on heterogeneous silicon. Their software traces a PyTorch workload, segments it into its component parts, and schedules each piece onto the best-suited hardware — connecting chips from different vendors on a single high-speed fabric.
In this interview, Gimlet co-founder Natalie Serrino and former Intel executive Beltir walk through the architecture (graph trace, optimal split points, lowering each segment to TensorRT on NVIDIA and equivalents elsewhere), the three customer segments they sell into (frontier labs, sovereign clouds, AI natives), and a concrete demo: on GPT-OSS 120B at 8K input / 1K output, running the speculative decoder on a d-Matrix Corsair card while NVIDIA B200s handle the verifier shifts the throughput-vs-interactivity Pareto frontier roughly 4× over GPU-only speculative decode.
The most surprising takeaway: most Neoclouds gave significant equity to a single silicon vendor in exchange for capacity. Hardware amortization is around 70% of their annual costs, and the equity terms prevent them from diversifying their silicon. So the only software innovation they can ship is disaggregation on top of one vendor's stack — never across vendors. Gimlet's two-track model (deploying orchestration software inside customer data centers, plus running their own Neocloud built on mixed silicon) is the answer to that constraint.
Read the full transcript on Chipstrat.
Chapters:
0:00 Intro and the chips no one's connected before
0:33 Inference cloud for agents
1:02 From Intel to Gimlet
2:14 The case for heterogeneous inference
4:03 Disaggregating inference by resource profile
6:24 Tracing PyTorch into a schedulable graph
8:08 Connecting chips never connected before
10:52 CPUs as the agentic workhorse
12:01 Tool calls in the same data center as the LLM
13:21 Latency vs throughput on a shared fabric
14:57 Three customer buckets
15:54 Sovereigns: make an API call, not a porting project
19:37 "Cracked software is the platform"
22:24 Why merchant silicon vendors need partners
25:18 Hyperscalers outsourcing CapEx, not just kernels
28:49 AI natives: latency budgets, not just price
32:06 The d-Matrix partnership
33:31 The Pareto frontier chart
35:56 Speculative decode on Corsair: 4× shift
37:27 4× faster, or 3× more customers?
41:22 Why most Neoclouds can't follow this model
42:34 Gimlet's two-track business model
44:30 CoreWeave vs Together vs Gimlet
45:15 Series A and hiring
Relevant reading:
The Information on Gimlet helping OpenAI optimize for Cerebras: https://www.theinformation.com/newsletters/ai-agenda/startup-helping-openai-optimize-ai-cerebras-chips
Sachin Katti and Zain Asgar coauthored research at Stanford: https://arxiv.org/abs/2507.19635
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X: https://x.com/chipstrat -
What's common to optics and power that ruins everything in the era of AI?
Resistance.
The same physics that drove interconnects to optics is now driving low-voltage power delivery up to 800V. Austin Lyons (Chipstrat) and Vik Sekar (Vik's Newsletter) unpack it using the Kyber rack as an example.
At 600kW and 48V, you're pushing 12,500 amps through a single rack. Power loss scales with I². The math doesn't work. The fix is 800V — and the parts come straight from the EV traction inverter ecosystem (SiC, GaN, IGBTs).
We cover the full grid-to-GPU power conversion chain (substation, utility room, PSU, intermediate bus converter, VRM), why vertical power delivery is the CPO equivalent for power, and why the power industry is a much wider open problem than optics or HBM. Plus the new topology fight: 800V → 48V (reuse the existing 48V infrastructure) vs 800V → 6V (skip 48V entirely, like TI and Navitas are pushing).
We also touch Coherent's six-inch indium phosphide ramp at Järfälla, Sweden, and why margins are the real read-through next quarter.
Relevant reading:
Vik's Substack post on power: https://www.viksnewsletter.com/p/power-delivery-as-the-next-physics-wall
Google TPU 8i / 8t blog (Boardfly deep dive): https://cloud.google.com/blog/products/compute/tpu-8t-and-tpu-8i-technical-deep-diveGet more of Austin and Vik daily, free! Sign up here: https://www.semidoped.com/
Follow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/austinsemisFollow Vik:
Newsletter: https://www.viksnewsletter.com/
X: https://x.com/vikramskrChapters
(00:00) Intro
(01:41) Memory tax: inflation, not innovation
(03:46) Boardfly: 16 hops to 7
(05:12) Coherent's six-inch indium phosphide ramp
(12:15) Power is the next physics wall
(15:08) Why 48V breaks at 600kW: 12,500 amps
(23:05) 800V and vertical power delivery: CPO for power
(30:34) Grid to GPU: every stage is a different supply chain
(39:20) 800V → 48V or skip straight to 6V? -
The hyperscaler memory tax quarter.
More CapEx? Pssh. We knew flops needed scaling.
But $25B at Microsoft alone just to pay higher component prices?
A memory tax. That's the news.
NAND? Sold out. HBM? Sold out.
What we cover:
SanDisk revenue +97% sequential.78% gross margin. Guidance above 80% next quarter.Samsung HBM4 first to ship. Demand outstripping supply.DeepSeek v4 goes SSD-centric. KV cache offloads to flash.Microsoft: $25B of 2026 CapEx is just memory pricing.Jassy: memory shortage pushes on-prem to AWS.Qualcomm: mystery custom ASIC. Ships December.New Semi Doped with @vikramskr and @austinsemis.
Check out our Substacks
- https://www.viksnewsletter.com/
- https://www.chipstrat.com/Chapters:
0:00 Intro and Vik goes full-time
5:15 Earnings week: the memory tax
7:26 Samsung HBM4 and the Gbps race
14:42 Is the memory tax worth it?
17:37 SanDisk and the SunDisk origin
23:22 78% gross margins and 5-year supply lock-ins
29:29 DeepSeek v4 and SSD-centric inference
38:49 Hyperscaler CapEx and the cloud pull
42:49 AI accelerators: TPU, Trainium, MTIA -
Google's Cloud Next 2026 keynote? Fire. 🔥
The TPU is now two chips instead of one — 8t for training, 8i for inference — but more interestingly, it's two scale-up networking topologies too.
Austin Lyons (Chipstrat) and Vik Sekar (Vik's Newsletter) walk through what actually changed, one day after the announcement. OCS? Yes. AECs? Yep. Copper? Yep. Optics? Yep.
We cover Virgo (Google's 47 petabit/second scale-out fabric, built entirely on OCS), Boardfly (the new scale-up topology for MoE inference that cuts hop count from 16 to 7), and the 3D torus Google still uses for training.
Why is optical circuit switching the substrate of Google's data center? Why do active electrical cables still carry scale-up traffic inside racks? Why did Google split the CPU layer too, with custom ARM Axion head nodes to keep the TPUs fed?
Along the way we trace the Dragonfly topology lineage to a 2008 paper by John Kim, Bill Dally, Steve Scott, and Dennis Abts. Abts went on to build Groq's rack-scale interconnect before landing at Nvidia.
Chapters:
0:00 Intro
0:21 Two TPUs for two workloads
2:31 HBM, SRAM, and Axion CPUs
7:22 Why networking is the new bottleneck
17:14 Virgo: rebuilding scale-out on optics
25:24 3D torus Rubik's Cube scale-up for training
34:50 Boardfly: scale-up for MoE inference
42:07 Workload-specific everythingFollow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/austinsemisFollow Vik:
Newsletter: https://www.viksnewsletter.com/
X: https://x.com/vikramskr -
Matt Steiner, VP of Monetization Infrastructure, Ranking & AI Foundations at Meta, walks through how Meta's ad system actually works, and why the infrastructure behind it differs from what you'd build for LLMs.
We cover Andromeda (retrieval on a custom NVIDIA Grace Hopper SKU Meta co-designed), Lattice (consolidating N ranking models into one), GEM (Meta's Generative Ads Recommendation foundation model), and the adaptive ranking model, a roughly one-trillion-parameter recommender served at sub-second latency.
We get into why recommender workloads aren't embarrassingly parallel like LLMs (the "personalization blob"), what that means for Meta's MTIA custom silicon roadmap, and how LLM-written kernels (KernelEvolve) flipped the economics of running a heterogeneous hardware fleet. Demand for software engineering has actually gone up as the price has come down. Meta now wants ~100x more optimized kernels per chip.
Read the full transcript at https://www.chipstrat.com/p/an-interview-with-meta-vp-matt-steiner
Chapters:
0:00 Intro and scale
0:39 How Meta's ad system works
2:00 Meta Andromeda and the custom NVIDIA SKU
3:30 Lattice: consolidating ranking models
5:00 GEM, Meta's ads foundation model
6:30 Adaptive ranking for power users
8:17 The scale: 3B DAUs at sub-second latency
9:40 Why longer interaction histories matter
10:45 The anniversary gift analogy
12:57 A decade of compute evolution
15:21 Meta's infra as a CP-SAT problem
16:07 Co-designing Grace Hopper with NVIDIA
17:47 Matching compute shape to workload
18:26 Influencing hardware and software roadmaps
20:23 MTIA: why ads aren't LLMs
22:07 The personalization blob and I/O ratios
26:38 One trillion parameters at sub-second latency
28:26 Heterogeneous hardware trade-offs
29:30 KernelEvolve: LLMs writing custom kernels
33:30 GenAI and recommender systems cross-pollination
35:21 The 2-year infrastructure outlook
37:00 Why demand for software engineering is rising
38:53 How Matt stays on top of it all
Relevant reading:
KernelEvolve (Meta Engineering): https://engineering.fb.com/2026/04/02/developer-tools/kernelevolve-how-metas-ranking-engineer-agent-optimizes-ai-infrastructure/
Follow Chipstrat:
Newsletter: https://www.chipstrat.com
X: https://x.com/chipstrat -
Austin and Vik discuss Credo's acquisition of Dust Photonics, XPO as the new standard for scale-out (maybe instead of CPO?) and some thoughts about Nuvacore entering the CPU scene for agentic AI.
Gavin Baker's tweet: https://x.com/GavinSBaker/status/2044410644301046031?s=20
Vik's Substack: https://www.viksnewsletter.com
Austin's Substack: https://www.chipstrat.com
Chapters
00:00 Introduction to the Semiconductor Landscape
02:49 The Rise of Nuvacore and CPU Innovations
05:27 The Demand for CPUs in the AI Era
07:59 Photonics: The Next Frontier in Semiconductors
10:26 Credo's Acquisition of Dust Photonics
13:12 Vertical Integration in Semiconductor Companies
15:15 The Future of Copper and Optical Technologies
20:28 The Evolution of AI Training Models
25:28 Innovations in Optical Interconnects
31:10 The Future of Data Center Connectivity
36:56 Strategic Implications in the Optical Ecosystem -
In this episode, Austin and Vik discuss if Intel is finally back with CPU partnerships with Google, and heterogeneous inference with SambaNova, while market cap soars above $300B. Vik tries to get his OpenClaw instance to dream every night.
Chapters
00:00 Anthropic's New Direction: Chip Development
02:30 Navigating Subscription Changes and Token Costs
05:25 Exploring Alternative AI Models
08:10 The Economics of AI: Rent vs. Buy
10:56 Intel's Resurgence and Market Dynamics
15:23 Intel's Strategic Partnerships and Market Positioning
19:37 The Role of IPUs in Modern Computing
25:08 Coexistence of x86 and ARM Architectures
29:55 Innovations in Chip Architecture and Future Prospects -
Reiner Pope is the co-founder and CEO of MatX, the startup building chips designed from first principles for LLMs. Before MatX, Reiner was on the Google Brain team training LLMs, and his co-founder Mike Gunter was on the TPU team. They left Google one week before ChatGPT was released.
A counterintuitive throughput insight from the conversation:
“Low latency means small batch sizes. That is just Little’s law. Memory occupancy in HBM is proportional to batch size. So you can actually fit longer contexts than you could if the latency were larger. Low latency is not just a usability win, it improves throughput.”
We get into:
• The hybrid SRAM + HBM bet, and why pipeline parallelism finally works
• Overcoming the CUDA moat
• Why frontier labs are willing to bet on an AI ASIC startup
• Memory-bandwidth-efficient attention, numerics, and what MatX publishes (and what it does not)
• Why 95% of model-side news is noise for chip design
• Why sparse MoE drives MatX to “the most interconnect of any announced product”
• How MatX uses AI for its own chip design
• The biggest challenges ahead
Chapters:
00:00 “We left Google one week before ChatGPT”
00:24 Intro: who is MatX
01:17 Origin story: leaving Google for LLM chips
02:21 GPT-3 and the “too expensive” problem
04:25 Why buy hardware that is not a GPU
05:52 Overcoming the CUDA moat
08:46 Early investors
09:35 The name MatX
09:59 The chip: matrix multiply + hybrid SRAM/HBM
12:11 Why pipeline parallelism finally works
14:22 Reading papers and Google going dark
15:20 Research agenda: attention and numerics
17:06 Five specs and meeting customers where they are
19:24 Why frontier labs are the natural first customer
20:32 Workloads: training, prefill, decode
22:18 Little’s law and the throughput case for low latency
24:29 Interconnect and MoE topology
26:35 Inside the team: 100 people, full stack
28:32 Agentic AI: 95% noise for hardware
30:35 KV cache sizing in an agentic world
32:11 How MatX uses AI for chip design (Verilog + BlueSpec)
34:23 Go to market: proving credibility under NDA
35:12 Porting effort for frontier labs
36:34 Biggest skepticism: manufacturing at gigawatt scale
37:32 Hiring plug
Austin Lyons @ Chipstrat: https://www.chipstrat.com
Vik Sekar @ Vik's Newsletter: https://www.viksnewsletter.com/
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Intel Foundry just partnered with Elon Musk’s Terafab. What is Terafab anyway, why vertically integrated fabs make sense but the economics don’t (yet!), and what Intel is doing here (hint: no idea).
Then: OpenAI acquires TBPN for an estimated $100-300M. Not sure why, but the more interesting thing is the value of niche audiences when five companies control a trillion dollars in AI capex.
And finally, Citrini Research sent an analyst to the Strait of Hormuz with a Pelican case full of spy gear, $15K cash, and Cuban cigars. The most unhinged research trip in Substack history.
Austin Lyons — Chipstrat (https://chipstrat.com) Vik Sekar — Vik's Newsletter (https://www.viksnewsletter.com)
Subscribe for weekly episodes on semiconductors, AI, infrastructure, and the business of chips.
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In this episode, Austin and Vik analyze NVIDIA's $2 billion investment in Marvell NVLink Fusion, exploring its implications for AI infrastructure, interconnect protocols, and the broader chip ecosystem. They also discuss the current memory market surge, DRAM pricing, and Intel's strategic fab buyback, providing deep insights into industry trends and future directions.
On Substack
Vik: https://www.viksnewsletter.com/
Austin: https://www.chipstrat.com/
Chapters
00:00 NVIDIA's $2 Billion Investment in Marvell
20:11 The Memory Market Crisis
20:16 The Future of Memory Pricing and Consumer Impact
22:55 The Cycle of Supply and Demand in Memory
27:23 AI's Impact on Memory Demand
31:46 Long-Term Agreements and Market Stability
35:07 Intel's Strategic Fab Buyback
40:44 Monopoly Analogy: Intel's Market Strategy -
In this episode, Austin and Vik analyze recent developments in GloFo patent lawsuits, the impact of TurboQuant on AI inference, and ARM's strategic move into silicon for agentic AI workloads.
Read Vik's substack: https://www.viksnewsletter.com
Read Austin's substack: https://www.chipstrat.com
Chapters
00:00 Patent Wars in Semiconductor Industry
07:14 Understanding TurboQuant and Its Implications
24:42 Innovations in Memory Management
28:00 The Rise of ARM AGI CPUs
32:56 Agentic AI and CPU Compatibility
39:54 Performance Metrics in Agentic AI
44:52 ARM's Market Timing and Challenges -
Austin and Vik break down a packed week in semiconductors, covering GTC, OFC, and Micron earnings. The conversation kicks off with Jensen Huang's bold claim that engineers should spend $250K/year on AI tokens, and whether companies will buy tokens or token generators (i.e., on-prem hardware like the Dell Pro Max with GB300). They dig into the CapEx vs OpEx tradeoffs, data security concerns, and how sharing GPU resources might end up looking a lot like the old EDA license model.
Next up: Micron crushed earnings and appears to be designed into Vera Rubin for HBM4 — despite months of rumors saying otherwise. Austin and Vik unpack the nuance around HBM pin speeds, memory node base dies, and what Micron's massive new fab investments in Taiwan, Singapore, Idaho, and New York mean for the memory cycle.
The back half of the episode dives into optical interconnects for AI scale-up. A new industry consortium (OCI-MSA) has formed with Meta, Broadcom, NVIDIA, and OpenAI to standardize optical components. Vik explains why traditional indium phosphide lasers might be overkill for short-reach scale-up, and makes the case for micro LEDs — a "slow but wide" approach that could fill the gap between copper and conventional optics. They also touch on Credo's expanding product portfolio (and the infamous purple-to-orange cable saga), plus Lumentum's new VCSEL work for scale-up.
Vik - https://www.viksnewsletter.com/
Austin - https://www.chipstrat.com/
CHAPTERS
0:00 Intro & GTC/OFC Conference Overload
2:09 Jensen's $250K Token Budget Per Engineer
5:08 On-Prem Inference vs. Cloud Token Spending (Dell Pro Max, CapEx vs OpEx)
6:44 Sharing GPU Resources Like EDA Licenses
8:16 Data Security & On-Prem Privacy Concerns
9:53 Matthew Berman's Fine-Tuned Open Claw Agent
10:35 Vik Sets Up Open Claw on a Home Server
11:53 Always Be Clauden (ABC) – Managing Agents from Your Phone
13:34 Micron Earnings & HBM4 in Vera Rubin
16:39 HBM Pin Speeds & the Micron Design-In Debate
20:17 Micron's New Fab Investments & Memory Cycle Fears
23:49 Why AI Drives a Step Change in Memory Demand
26:30 Optical Compute Interconnect MSA (OCI-MSA)
29:48 Scale-Up Optics: Do We Need New Technology?
30:58 Micro LEDs – The "Slow but Wide" Approach
35:45 Micro LEDs vs. Copper vs. Traditional Optics
36:55 Credo's Product Spectrum & the Purple Cable Story
39:31 VCSELs & Lumentum's 1060nm Scale-Up Play -
Vik and Austin unpack the Nvidia GTC keynote with fresh, top-of-mind takes while trying to breakdown key announcements, what matters and what doesn't. They discuss Groq's LPX, optics+copper for scale up, new CPU requirements, CPO for networking, and what agents means for software, and much, much, more.
Check out Austin's substack: https://www.chipstrat.com
Check out Vik's substack: https://www.viksnewsletter.com
Chapters
00:00 Introduction and Keynote Context
03:18 Keynote Highlights and Gaming Innovations
06:18 Generative AI: The Three Eras
09:28 Inference: The New Revenue Generator
12:21 NVIDIA's Tiered Approach to AI Models
15:30 The Grok Chip and Its Role
18:35 Vera Rubin System: A Full Data Center
21:18 CPU Demand and Performance
24:31 Networking Innovations and Future Directions
32:32 Innovations in PCB Technology
34:06 Scaling GPU Systems
36:57 Understanding the STX Rack and AI Storage
38:23 The Rosa CPU and Its Significance
40:07 Digital Twin Platforms and AI Factories
43:53 NVIDIA's New Software Innovations
47:09 The Future of Token Budgets in AI
54:15 Balancing CapEx and OpEx in AI Deployments -
Austin recaps moderating an agentic AI panel at Synopsys Converge, then gives an in-depth technical breakdown of Meta's MTIA custom silicon. Why they're building it, how chiplets let them ship a new chip every 6 months, and how the roadmap is shifting toward gen AI inference. Vik digs into Applied Optoelectronics (AAOI), the vertically integrated Texas laser shop whose stock went from $1.48 to $100+, and whether history is about to rhyme.
Austin Lyons: https://www.chipstrat.com
Vik Sekar: https://www.viksnewsletter.com/
Topics covered:
• Agentic AI in chip design — how it changes roles for junior and senior engineers
• Optical circuit switching and what it means for Arista's business model
• Meta's ad-serving pipeline: Andromeda, Lattice, and the GEM foundation model
• Why custom silicon (MTIA) makes sense at Meta's scale
• MTIA chiplet strategy — 4 generations in 2 years
• AAOI's vertical integration, Amazon's $4B warrant deal, and the 2017 parallel
Chapters:
0:00 Intro
1:26 Synopsys Converge — Agentic AI Panel
9:44 Vik's Article: Optical Circuit Switching & Arista
14:43 Meta MTIA — A New Chip Every 6 Months
21:32 Why Custom Silicon Makes Sense for Meta
27:22 MTIA Chiplet Strategy & Roadmap
33:56 Gen AI Fits Meta's Business Model
36:31 How Meta Ships Chips So Fast
40:30 Applied Optoelectronics (AAOI) Deep Dive
45:02 Amazon's $4B Warrant Deal
48:54 Can AAOI's Lasers Compete with Lumentum?
53:16 AAOI's Aggressive Capacity Buildout
55:35 History Rhymes: AAOI's 2017 Boom & Bust
1:00:55 Wrap-Up
#semiconductors #chips #tech #meta #MTIA #AAOI #optics #inference #AI -
This week, Austin and Vik break down the optics vs. copper debate that rocked semis this week. Nvidia dropped $4 billion on Lumentum and Coherent, Credo posted a blowout quarter betting on copper, and then Hock Tan shocked everyone claiming 400G per lane works over copper in Broadcom’s labs — potentially pushing CPO out to 2030+. Plus, Vik’s 4D chess conspiracy theory on why Hock Tan is talking up copper when Broadcom is a CPO company.
Like, subscribe, and drop your thoughts on the copper vs. optics debate in the comments!
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* Chipstrat by Austin Lyons — chipstrat.com
* Vik’s Semiconductor Newsletter by Vik Sekar — viksnewsletter.comChapters
(00:00) - Newsletter Plugs: Groq LPUs & Broadcom’s Laser Business
(03:15) - Dynamo & the Rise of Workload-Specific Hardware
(08:04) - Austin’s Broadcom Laser Deep Dive
(09:53) - The Week’s Whiplash: Optics Monday, Copper Wednesday
(17:50) - Why Nvidia Invested $4B: Geopolitics, Supply & the HBM Playbook
(24:15) - CPO Lasers & Optical Circuit Switches
(26:16) - Credo Earnings: 200% YoY Growth & the Copper Bull Case
(31:09) - Reliability, AECs & Oracle’s GPU Cluster Problem
(35:48) - Credo’s Optics Play: Micro-LED Active Cables & the CPO Timing Risk
(38:45) - Broadcom Earnings: Hock Tan’s Copper Bombshell
(43:34) - Customer-Owned Tooling: Hock Tan Says “Good Luck”
(44:25) - Vik’s 4D Chess Theory: Why Hock Tan Talks Up Copper
(47:03) - Wrap-Up: It’s Both — The Real Question Is Timing -
This week, we move from optics technology to optics companies. We walk the AI optical supply chain from bottom to top. Main debate: Who has a moat? Who is already priced for perfection? *Not investment advice, do your own due diligence*
AXTI - Indium phosphide substrate supplier. Critical bottleneck in the laser stack. Major China export-control risk. Massive stock run vs thin earnings.
Tower Semiconductor - Leading silicon photonics foundry. 5x capacity expansion with customer prepayments. Strong process lock-in. Pure-play optics exposure.
GlobalFoundries - 300mm monolithic photonics platform + Chips Act support. Optics growing fast but still small piece of overall business.
Lumentum - Dominant EML laser supplier. Explosive AI demand. Strong technical moat. Valuation and capex sensitivity are key risks.
Coherent - Vertically integrated from substrate to module. 6-inch InP push could lower costs structurally. Execution and margin mix matter.
Fabrinet - Optics assembly partner. High NVIDIA exposure. Scales with industry, but dependent on upstream supply.
Corning - AI data centers require far more fiber than traditional cloud. $6B Meta deal adds visibility. Timing of scale-up optics is the swing factor.
Timestamps
00:01 Intro
06:59 AXT $AXTI
13:38 Tower Semiconductor $TSEM
23:58 GlobalFoundries $GFS
32:43 Lumentum $LITE
39:38 Coherent $COHR
47:09 Fabrinet $FN
54:07 Corning $GLWAustin's Substack: https://www.chipstrat.com/
Vik's Substack: https://www.viksnewsletter.com/
- Visa fler
